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Hi-end DSP System
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The
PowerFFT™ is the world's fastest and most powerful
FFT-centric floating-point DSP, able to process 100 million
complex samples per second in continuous, sustained mode,
with a rich set of functionalities for Fast-Fourier Transforms
(FFT) computations and FFT-based algorithms, including
n-dimensional FFTs, correlations and convolutions.
The PowerFFT™ is available on a choice of boards
(VME, PCI64) for lowest-latency high data rate, high bandwidth,
high throughput applications and systems.
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| (PowerFFT™ in a Race++ daughter-card)
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One-dimensional: The stand-alone PowerFFT™
processor chip is capable of executing sustained FFT processing,
vector multiplication convolutions and correlations on 1D complex
data sets of 1K samples. With its addressing FPGA (Eonic's patented
memory controller), the PowerFFT™ is able of sustained
FFT processing, vector multiplication convolutions and correlations
on 1D complex data sets of 1M (one million) samples and above.
Competing products never really match the computing power of
the PowerFFT™.
Multi-dimensional: The PowerFFT has additional data ports
for 4 SDRAM banks for long FFT processing or multidimensional
FFT-based processing. Port 0 is the 64 bit primary input port,
Port 5 is the 64 bit primary output port, and Port 1…4 can be
connected to SDRAM banks to handle corner turning operations
or act as double buffers. An addressing FPGA takes care of the
SDRAM addressing (including refresh if necessary), so that the
FFT processor is independent of the external memory type, yet
allows much higher memory densities than with more expensive
SRAM.
FFT processor programming is performed through instruction sets.
The instructions determine the data flow and the memory addresses
to be generated by the addressing FPGA. Depending on the user
calls (one call can be, for example, the convolution of a 256
X 256 kernel with a 512 x 512 data set), a proper instruction
set is selected for the FFT chip.
Basically, one instruction contains the following information:
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mode of the FFT core / vector multiplier; length of the
data vectors
data
transfer settings: |
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1. target port of the input Port 0 data vector
2. source port of the output Port 5 data vector
3. source and target port of the vector to be processed
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In this way, many FFT operations can be mapped on the PowerFFT™
processor by sequencing PowerFFT™ instructions. Basic instruction
sets for representative operations, such as listed in the table,
are preprogrammed. User/application-specific multidimensional
FFT-based operations are implemented by downloading specific
instruction sets.
Development environment: a generic, GUI-based, simple
and intuitive development environment supports the PowerFFT™
and delivers effective yet simple programming, debugging, simulating
and operating the PowerFFT™. See its description and manual
in the Downloads section.
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| (The PowerFFT™ in its FBGA packaging) |
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| Main features and benefits |
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World’s fastest stand-alone full-floating point FFT ASIC
(1K complex point FFT in 10 μs, incl. windowing at 100
MSPS sustained throughput)
64 bit
input port, 64 bit output port, and 4 additional I/O ports
for 4 SDRAM (or SRAM) bank extension for long FFTs, FFT
based multi-dimensional algorithms, overlapped algorithms,
and (double buffered) corner turning operations
Address
Generator FPGA allows cost-effective memory use, easy
upgrades to larger memories, and specialized memory use
for space and military applications
Instruction
sets available for FFT macro-functions (=1M pts. 1D FFT
/ convolution / correlation, =1K × 1K pts. 2D FFT / convolution
/ correlation)
Upgrade
instruction sets available for large (> 1M pts.) 1D,
(>1K × 1K pts.) 2D and multi-dimensional FFT-based
algorithms (user specific)
100 MHz
I/O clock, 128 MHz internal clock, 3.3/1.8 V operation,
< 2 W power dissipation, 0.18μ CMOS standard cell process
Extensive
data format support:
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standards: 32 bit IEEE floating point, 32 bit integer,
16 bit integer (all parallel and sequential I&Q)
specials: 16 and 32 bit sign inverted integer (parallel
and sequential I&Q), 2×24+9 bits hybrid floating
point, 2×12+8 bits hybrid floating point |
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NB: all performance figures
have been measured on PCI 64 board during sustained, continuous
execution of FFT algorithms, using standard SDRAM banks,
including RAM access latency times. No data from simulations
here.
Status
Currently available as off-the-shelf component. |
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| DSP Development Solutions |
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Lyrtech offers a comprehensive line of DSP and
FPGA development solutions that provide increased performance,
cost effectiveness and overall efficiency in the development
of digital signal processing systems.
We also offer complete integration with system-level software
simulation tools such as MATLAB/Simulink and Real-Time Workshop
from The MathWorks and System Generator for DSP from Xilinx.
Features and Benefits of Lyrtech DSP Products
DSP and FPGA
integration on the same board-level solution
DSP+FPGA hardware-in-the-loop
co-simulation and real-time implementation capabilities of Simulink
and System Generator models
Communication
over wired and wireless Local and Wide Area Networks (LAN &
WAN)
On-board unique
Ethernet JTAG tool for debugging and communication through a
LAN/WAN
Access to multiple
I/O interfaces (VIM-2, GPIO, Codec) and access to a large number
of pre-packaged compatible I/O modules
Access to all
required low-level drivers and system-level toolboxes for use
within Simulink for HOST, DSP-FPGA board-level solutions and
I/O modules
Access to reference
designs for rapid development
SignalMaster Family
Lyrtech offers you the best hardware-in-the-loop solutions for
the development of digital signal processing (DSP) systems and
applications. The SignalMasterT product line offers you stand-alone
/cPCi, open and reconfigurable development solutions integrating
CPU, DSP and FPGA processor technology and more features that
will be of interest depending on your area of application.
如果您需要更为详细的系统和产品信息，请联系我们，我们将为您提供详细产品信息。
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